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September 19, subject to adjustment as described in the accompanying Equity Index Underlying Supplement. The early redemption payment will be an amount equal to i the stated principal amount plus ii the contingent quarterly payment with respect to the related determination date. With respect to each underlying index, its official closing level on any determination date other than the final determination date, as determined by the calculation agent.

The securities will not be listed on any securities exchange. Commissions and issue price: With respect to each determination date other than the final determination date, the 3rd business day after the related determination date. The payment of the contingent quarterly payment, if any, with respect to the final determination date will be made on the maturity date.

With respect to each underlying index, its official closing level on the pricing date. With respect to each underlying index, its official closing level on the final determination date. Worst performing underlying index: The underlying index with the largest percentage decrease from its initial index level to its final index level.

The estimated initial value of the securities will be less than the price you pay to purchase the securities. The estimated initial value does not represent a minimum price at which we or any of our affiliates would be willing to purchase your securities in the secondary market, if any, at any time. The estimated initial value will be calculated on the pricing date and will be set forth in the pricing supplement to which this free writing prospectus relates.

Hypothetical Initial Index Level:. With respect to each underlying index, In Example 1 , the securities are automatically redeemed following the 1st determination date as the determination closing level of each underlying index on the 1st determination date is greater than or equal to its initial index level.

You would receive the early redemption payment, calculated as follows:. You would receive no contingent payment with respect to the 2nd through the 9th determination date, since the determination closing level of at least one underlying index on each of those determination dates is less than its.

The securities are automatically redeemed following the 10th determination date, as the determination closing level of each underlying index on that day is greater than or equal to its initial index level. In Example 3 , the closing level of at least one underlying index is below its coupon barrier level on every determination date. As a result, you would not receive any contingent quarterly payments during the term of the securities and, at maturity, you would be fully exposed to the decline in the closing level of the RTY, which is the worst performing underlying index.

As the final index level of the worst performing underlying index is less than its downside threshold level, your payment at maturity is calculated as follows:. In Example 4 , the closing level of at least one underlying index is below its coupon barrier level on each of the 1st through the 11th determination date. As a result, the contingent quarterly payment is not payable for any of those determination dates. At maturity, because the final index level of each underlying index is greater than its downside threshold level, you would receive the stated principal amount.

However, because neither of the underlying indices is less than its coupon barrier level, you would also receive the contingent quarterly payment with respect to the final determination date. You may lose your entire initial investment. The securities do not guarantee any return of principal.

The securities differ from ordinary debt securities in that we will not necessarily pay the full principal amount of the securities at maturity. HSBC will only pay you the principal amount of your securities at maturity if the securities have not been automatically redeemed prior to maturity and the final index level of each underlying index is greater than or equal to its downside threshold level.

If the final index level of any underlying index is less than its respective downside threshold level, you will be exposed to the decline in the closing level of the worst performing underlying index, as compared to its initial index level, on a 1 to 1 basis and you will receive for each security that you hold at maturity an amount equal to the stated principal amount times the index performance factor of the worst performing underlying index. You will not receive any contingent quarterly payment for any quarterly period where the determination closing level or the final index level, as applicable, of any underlying index is less than its respective coupon barrier level on the related determination date.

A contingent quarterly payment will be made with respect to a quarterly period only if the determination closing level or the final index level of each underlying index is greater than or equal to its coupon barrier level on the related determination date. It is possible that the closing level of each underlying index could be below its respective coupon barrier level on most or all of the determination dates so that you will receive few or no contingent quarterly payments.

Investors will not participate in any appreciation of any underlying index, and your return on the securities is limited to the principal amount plus any contingent quarterly payments, regardless of any appreciation in the levels of the underlying indices. Investors will not participate in any appreciation of any underlying index from its initial index level.

Unless the final index level of any underlying index is less than its coupon barrier level, you will receive at maturity the stated principal amount plus the contingent quarterly payment with respect to the final determination date, regardless of any appreciation in the levels of the underlying indices, which may be significant. The return on the securities will be limited to the contingent quarterly payment that is payable with respect to each determination date on which the determination closing level or the final index level, as applicable, of each underlying index is greater than or equal to its coupon barrier level.

Accordingly, the return on the securities may be significantly less than the return on a direct investment in the securities comprising the underlying indices during the term of the securities. The securities may be called prior to the maturity date. If the securities are called early, the holding period over which you will receive contingent quarterly payments could be as little as 3 months.

If the securities are redeemed prior to the maturity date, you will receive no more contingent quarterly payments. There is no guarantee that you would be able to reinvest the proceeds from an investment in the securities at a comparable return for a similar level of risk following an automatic call. You are exposed to the market risk of all underlying indices, with respect to both the contingent quarterly payments, if any, and the payment at maturity, if any.

Your return on the securities is not linked to a basket consisting of the 2 underlying indices. Rather, it will be contingent upon the independent performance of each underlying. Unlike an instrument with a return linked to a basket of underlying assets, in which risk is potentially mitigated and diversified among all the components of the basket, you will be exposed to the risks related to both of the underlying indices. Poor performance by any underlying index over the term of the securities may negatively affect your return and will not be offset or mitigated by any positive performance by the other underlying index.

To receive any contingent quarterly payments, all underlying indices must close at or above their respective coupon barrier levels on the applicable determination date. In addition, if any underlying index has decreased to below its respective downside threshold level as of the final determination date, you will be fully exposed to the decrease in the worst performing underlying index on a 1 to 1 basis, even if the other underlying index has appreciated.

Accordingly, your investment is subject to the market risk of each of the underlying indices. Because the securities are linked to the performance of the worst performing underlying index, you are exposed to greater risks of receiving no contingent quarterly payments and sustaining a significant loss on your investment than if the securities were linked to just one underlying index.

The risk that you will not receive any contingent quarterly payments, or that you will suffer a significant loss on your investment, is greater if you invest in the securities as opposed to substantially similar securities that are linked to the performance of just one underlying index. With 2 underlying indices, it is more likely that one or both of the underlying indices will close below their respective coupon barrier levels on any determination date including the final determination date and below its downside threshold level on the final determination date, than if the securities were linked to only one underlying index.

Therefore, it is more likely that you will not receive any contingent quarterly payments, and that you will suffer a significant loss on your investment. In addition, because each underlying index must close above its initial index level on a quarterly determination date in order for the securities to be called prior to maturity, the securities are less likely to be called than if the securities were linked to just one underlying index.

The amounts payable on the securities are not linked to the levels of the underlying indices at any time other than on the determination dates, including the final determination date. The payments on the securities will be based on the closing levels of the underlying indices on each determination date, subject to postponement for non-trading days and certain market disruption events.

Even if the level of an underlying index appreciates prior to an applicable determination date but then drops on that day to a level that is below its coupon barrier level, the contingent quarterly payment on the securities will not be payable for that determination date.

Similarly, even if the level of an underlying index appreciates prior to the final determination date but then decreases on that day to a level that is below its downside threshold level, the payment at maturity will be less, and may be significantly less, than it would have been had the securities been linked to the levels of the underlying indices on a date prior to the final determination date. Although the actual levels of the underlying indices on the maturity date or at other times during the term of the securities may be higher than their levels on one or more determination dates, the payments on the securities will be based solely on the levels of the underlying indices on the determination dates.

The market price of the securities will be influenced by many unpredictable factors. The level of each underlying index may be, and has recently been, volatile, and we can give you no assurance that the volatility will lessen. You may receive less, and possibly significantly less, than the stated principal amount if you try to sell your securities prior to maturity.

The securities are senior unsecured debt obligations of the Issuer, HSBC, and are not, either directly or indirectly, an obligation of any third party. As further described in the accompanying prospectus supplement and prospectus, the securities will rank on par with all of the other unsecured and unsubordinated debt obligations of HSBC, except such obligations as may be preferred by operation of law. Any payment to be made on the securities depends on the ability of HSBC to satisfy its obligations as they come due.

As a result, the actual and perceived creditworthiness of HSBC may affect the market value of the securities and, in the event HSBC were to default on its obligations, you may not receive the amounts owed to you under the terms of the securities and could lose your entire investment.

Investing in the securities is not equivalent to investing in the securities comprising the underlying indices. Investing in the securities is not equivalent to investing in the component securities of any underlying index.

Investors in the securities will not have voting rights or rights to receive dividends or other distributions or any other rights with respect to the securities comprising the underlying indices. The RTY tracks companies that may be considered small-capitalization companies. These companies often have greater stock price volatility, lower trading volume and less liquidity than large-capitalization companies and therefore the respective index level may be more volatile than an investment in stocks issued by larger companies.

Stock prices of small-capitalization companies may also be more vulnerable than those of larger companies to adverse business and economic developments, and the stocks of small-capitalization companies may be thinly traded, making it difficult for the RTY to track them. In addition, small-capitalization companies are often less stable financially than large-capitalization companies and may depend on a small number of key personnel, making them more vulnerable to loss of personnel.

Small-capitalization companies are often subject to less analyst coverage and may be in early, and less predictable, periods of their corporate existences. These companies tend to have smaller revenues, less diverse product lines, smaller shares of their product or service markets, fewer financial resources and competitive strengths than large-capitalization companies, and are more susceptible to adverse developments related to their products.

Adjustments to any underlying index could adversely affect the value of the securities. The publisher of an underlying index may add, delete or substitute the securities comprising the relevant underlying index.

In addition, the publisher of an underlying index may make other methodological changes that could change the level of that underlying index. Further, the publisher of an underlying index may discontinue or suspend calculation or publication of that underlying index at any time. Any such actions could affect the value of and the return on the securities. The securities will not be listed on any securities exchange and secondary trading may be limited.

Therefore, there may be little or no secondary market for the securities. Even if there is a secondary market, it may not provide enough liquidity to allow you to trade or sell the securities easily. Because we do not expect that other broker-dealers will participate significantly in the secondary market for the securities, the price at which you may be able to trade your securities is likely to depend on the price, if any, at which HSBC Securities USA Inc. Accordingly, you should be willing to hold your securities to maturity.

Higher contingent quarterly payments or lower downside threshold levels are generally associated with underlying indices with greater expected volatility and therefore can indicate a greater risk of loss. The greater the expected volatility with respect to the underlying indices on the pricing date, the higher the expectation as of the pricing date that the levels of the underlying indices could close below their respective downside threshold levels on the final determination date, indicating a higher expected risk of loss on the securities.

This greater expected risk will generally be reflected in a higher contingent quarterly payment than the yield payable on our conventional debt securities with a similar maturity, or in more favorable terms such as a lower downside threshold level or a higher contingent quarterly payment than for similar securities linked to the performance of the underlying indices with a lower expected volatility as of the pricing date.

You should therefore understand that a relatively higher contingent quarterly payment may indicate an increased risk of loss. Further, a relatively lower downside threshold level may not necessarily indicate that the securities have a greater likelihood of a repayment of principal at maturity. The volatility of the underlying indices can change significantly over the term of the securities. The levels of the underlying indices for your securities could fall sharply, which could result in a significant loss of principal.

You should be willing to accept the downside market risk of the underlying indices and the potential to lose some or all of your principal at maturity. The estimated initial value of the securities, which will be determined by us on the pricing date, will be less than the price to public and may differ from the market value of the securities in the secondary market, if any.

The estimated initial value of the securities will be calculated by us on the pricing date and will be less than the price to public. The estimated initial value will reflect our internal funding rate, which is the borrowing rate we pay to issue market-linked securities, as well as the mid-market value of the embedded derivatives in the securities.

This internal funding rate is typically lower than the rate we would pay when we issue conventional fixed or floating rate debt. As a result of the difference between our internal funding rate and the rate we would use when we issue conventional fixed or floating rate debt securities, the estimated initial value of the securities may be lower if it were based on the prices at which our fixed or floating rate debt securities trade in the secondary market.

In addition, if we were to use the rate we use for our conventional fixed or floating rate debt issuances, we would expect the economic terms of the securities to be more favorable to you.

These pricing models consider certain assumptions and variables, which can include volatility and interest rates. Different pricing models and assumptions could provide valuations for the securities that are different from our estimated initial value. These pricing models rely in part on certain forecasts about future events, which may prove to be incorrect.

The estimated initial value does not represent a minimum price at which we or any of our affiliates would be willing to purchase your securities in the secondary market if any exists at any time.

This temporary price difference may exist because, in our discretion, we may elect to effectively reimburse to investors a portion of the estimated cost of hedging our obligations under the securities and other costs in connection with the securities that we will no longer expect to incur over the term of the securities.

We will make such discretionary election and determine this temporary reimbursement period on the basis of a number of factors, including the tenor of the securities and any agreement we may have with the distributors of the securities. The amount of our estimated costs which we effectively reimburse to investors in this way may not be allocated ratably throughout the reimbursement period, and we may discontinue such reimbursement at any time or revise the duration of the reimbursement period after the original issue date of the securities based on changes in market conditions and other factors that cannot be predicted.

The price of your securities in the secondary market, if any, immediately after the pricing date will be less than the price to public. The price to public takes into account certain costs.

These costs, except for the underwriting discount, will be used or retained by us or one of our affiliates.

If you were to sell your securities in the secondary market, if any, the price you would receive for your securities may be less than the price you paid for them because secondary market prices will not take into account these costs. The price of your securities in the secondary market, if any, at any time after issuance will vary based on many factors, including the levels of the underlying indices and changes in market conditions, and cannot be predicted with accuracy.

The securities are not designed to be short-term trading instruments, and you should, therefore, be able and willing to hold the securities to maturity.

Any sale of the securities prior to maturity could result in a loss to you. Hedging and trading activity by our affiliates could adversely affect the value of the securities. As a result, these entities may be unwinding or adjusting hedge positions during the term of the securities, and the hedging strategy may involve greater and more frequent dynamic adjustments to the hedge as the final determination date approaches.

Some of our affiliates may also trade the component securities and other financial instruments related to one or more underlying indices on a regular basis as part of their general broker-dealer and other businesses.

Any of these hedging or trading activities on or prior to the pricing date could potentially increase the initial index level of an underlying index and, as a result, its coupon barrier level, which is the level at or above which that underlying index must close on each determination date in order for you to earn a contingent quarterly payment or, if the securities are not called prior to maturity, its downside threshold level in order for you to avoid being exposed to the negative performance of the worst performing underlying index at maturity.

Additionally, such hedging or trading activities during the term of the securities could adversely affect the level of an underlying index on the determination dates and, accordingly, whether the. The calculation agent, which is HSBC or one of its affiliates, will make determinations with respect to the securities. As calculation agent, HSBC or one of its affiliates will determine the initial index level, the coupon barrier level, the downside threshold level and the final index level of each underlying index, whether the contingent quarterly payment will be paid on each contingent payment date, whether the securities will be redeemed following any determination date, whether a market disruption event has occurred with respect to an underlying index, and the payment that you will receive upon an automatic early redemption or at maturity, if any.

Moreover, certain determinations made by HSBC or one of its affiliates in its capacity as calculation agent, may require it to exercise discretion and make subjective judgments, such as with respect to the occurrence or non-occurrence of market disruption events. These determinations, which may be subjective , may adversely affect the payout to you upon an automatic early redemption or at maturity , if any. The securities are not insured by any governmental agency of the United States or any other jurisdiction.

The securities are not deposit liabilities or other obligations of a bank and are not insured by the Federal Deposit Insurance Corporation or any other governmental agency or program of the United States or any other jurisdiction. An investment in the securities is subject to the credit risk of HSBC, and in the event that HSBC is unable to pay its obligations as they become due, you may not receive the full amounts due on the securities. There is no direct legal authority as to the proper treatment of the securities for U.

Events of default and acceleration:. The following summary is a general discussion of the material U. This discussion applies only to initial investors in the securities who: Holders, as defined below, whose functional currency is not the U.

As the law applicable to the U. Moreover, the effect of any applicable state, local or non-U. This discussion is based on the Code, administrative pronouncements, judicial decisions and final, temporary and proposed U. Treasury Department regulations, all as of the date hereof, changes to. Persons considering the purchase of the securities should consult their tax advisors with regard to the application of the U.

There is no direct legal authority as to the proper tax treatment of the securities, and therefore significant aspects of the tax treatment of the securities are uncertain as to both the timing and character of any inclusion in income in respect of the securities. Under one approach, a security could be treated as a single financial contract that provides for a contingent quarterly payment.

Subject to the limitations described herein, and based on certain factual representations received from us, in the opinion of our special U. Due to the absence of statutory, judicial or administrative authorities that directly address the treatment of the securities or instruments that are similar to the securities for U.

Accordingly, you should consult your tax advisor regarding all aspects of the U. Unless otherwise stated, the following discussion is based on the treatment of each security as described in the previous paragraph. If one or more of the entities whose stock is included in an underlying index were so treated, certain adverse U. You should refer to information filed with the SEC and other authorities by the entities whose stock is included in an underlying index, and consult your tax advisor regarding the possible consequences to you if one or more of the entities whose stock is included in an underlying index is or becomes a PFIC or a USRPHC.

Tax Consequences to U. This section applies to you only if you are a U. Tax Treatment of the Securities. Many data accesses use addresses computed by adding a displacement to the value of a base address register. Using a displacement to cross one of the segment boundaries is not allowed and if attempted causes a MEM trap. This restriction allows direct determination of the accessed segment from the base address.

Physical Memory Attributes The physical memory attributes of segments zero to seven are implementation dependent. If an MMU is present and enabled, segments [0H - 7H] are considered virtual addresses that must be translated. If an MMU is not present the access characteristics are implementation dependent and may cause a trap.

Physical memory addresses in segment FH are guaranteed to be peripheral space and therefore all accesses are non-speculative and are not accessible to User-0 mode. The base location of this 64 KBytes space is implementation-dependent.

Segments 8H to DH have further limitations placed upon them in some implementations. For example, specific segments for program and data may be defined by device-specific implementations. Other details of the memory mapping are implementation-specific. For more information see. However it does not return a value, so it can not be used as an atomic "test and set" type operations for binary semaphores.

W is provided for this purpose. T instruction must lie within a range which has both read and write permissions enabled. The simple data elements are 8-bits, bits, bits, or bits wide. The architecture supports seven addressing modes. It is possible for an address register to be both the target of a load and an update associated with a particular addressing mode.

In the following case for example, the contents of the address register are not architecturally defined: This is true for all addressing modes in which there is an update of the address register. Absolute addressing uses an bit constant specified by the instruction as the memory address. The full bit address results from moving the most significant 4 bits of the bit constant to the most significant bits of the 32bit address Figure Other bits are zero-filled.

In this mode the offset is a bit sign-extended value. This allows any location in memory to be addressed using a two instruction sequence. The pre-increment addressing mode uses the sum of the address register and the sign-extended bit offset both as the effective address and as the value written back into the address register. Furthermore, the two versions of the mode may be used to pop from a downward-growing or upward-growing stack, respectively.

The post-increment addressing mode uses the value of the address register as the effective address and then updates this register by adding the sign-extended bit offset to its previous value. The most significant half of the odd register is the buffer size L. The least significant half holds the index into the buffer I.

The index is post-incremented using the following algorithm: To illustrate the use of circular addressing, consider a circular buffer consisting of 25, bit values. If the current index is 48, then the next item is obtained using an offset of two 2-bytes per value.

If we are at an index of 48 and use an offset of four, the new value of the index is two. In the end case, where a memory access runs off the end of the circular buffer Figure , the data access also wraps around to the start of the buffer. If a load word is performed using the circular addressing mode and the effective address of the operation points to element n, the bit result contains element n in the bottom 16 bits and element 0 in the top 16 bits.

An implementation is free to advise the user of optimal alignment of circular buffers etc. The length of the buffer must be a multiple of the data size, where the data size is determined from the instruction being used to access the buffer. For example, a buffer accessed using a load-word instruction must be a multiple of 4 bytes in length, and a buffer accessed using a load double-word instruction must be a multiple of 8-bytes in length.

If these restrictions are not met the implementation takes an alignment trap ALN. X n is data point n. Wn is twiddle factor n. The least-significant half of the odd register is the index into the array I. The most-significant half is the modifier M , used to update I after every access. To illustrate for a point real FFT using bit values, the buffer size is bytes. Stepping through this array using a bit-reverse index would give the sequence of byte indices: This sequence can be obtained by initializing I to 0 and M to H.

A instruction Add Scaled Index to Address , which adds a scaled data register to an address register. The scale factor can be 1, 2, 4 or 8 for addressing indexed arrays of bytes, half-words, words, or double-words.

The two low-order bits of the resulting byte address are cleared to give the address of the word containing the indexed bit. To extract the bit, the word in which it is contained, is loaded. The bit index is then used in an EXTR. A bit field, beginning at the indexed bit position, can also be extracted. However the architecture does not support direct PC-relative addressing of data. This is because the separate on-chip instruction and data memories make data access to the program memory expensive.

Once the base register is loaded it can be used to address other PC-relative data items nearby. A code address can be loaded into an address register in various ways. If the code is statically linked as it almost always is for embedded systems , then the absolute address of the code label is known and can be loaded using the LEA instruction Load Effective Address , or with a sequence to load an extended absolute address. The absolute address of the PC relative data is also known, and there is no need to synthesize PC-relative addressing.

For code that is dynamically loaded, or assembled into a binary image from position-independent pieces without the benefit of a relocating linker, the appropriate way to load a code address for use in PC-relative data addressing is to use the JL Jump and Link instruction. A jump and link to the next instruction is executed, placing the address of that instruction into the return address RA register A[11]. Before this is done though, it is necessary to copy the actual return address of the current function to another register.

The GPRs consist of 16 general purpose data and 16 general purpose address registers. The CSFRs control the operation of the core and provide status information about the core.

Where they are not given, the values are implementation specific. In the operational state only a subset of CSFRs can be modified in this way. All other functions remain identical between these states. The transition between the initialisation state and the operational state is controlled by the system implementation.

This facility adds an extra level of protection to critical CSFRs by only allowing them to be changed in the initialisation state.

Several instructions allow the interchange of information between data and address registers used for example, to create or derive table indexes. Two consecutive even-odd data registers can be concatenated to form eight extended-size registers E[0], E[2], E[4], E[6], E[8], E[10], E[12], and E[14] , in order to support bit values.

Registers A[0], A[1], A[8], and A[9] are defined as system global registers. Their contents are not saved or restored across calls, traps or interrupts. While the bit instructions have unlimited use of the GPRs, many bit instructions implicitly use A[15] as their address register and D[15] as their data register. This implicit use eases the encoding of these instructions into 16 bits. For example, E[8] is the concatenation of D[9] and D[8], where D[8] is the least significant word of E[8].

There are no separate floating-point registers. The data registers are used to perform floating-point operations. The floating-point data is saved and restored automatically using the fast context switch support. Figure shows the bit wide GPRs. Registers A[10] to A[15] and D[8] to D[15] are part of the upper context. Upper and lower contexts are described in detail in Chapter 4. The PC should only be written when the core is halted. If the core is not in halt a write will have no effect.

The lower half holds control values and parameters related to the protection system, including: These bits may be set or cleared as execution side effects of user instructions.

The memory protection register values control load, store and instruction fetches within the current process. Protection Register Set 0 01B: Protection Register Set 1 10B: Protection Register Set 2 11B: User-0 Mode No peripheral access. This access level is given to tasks that need not directly access peripheral devices.

Tasks at this level do not have permission to enable or disable interrupts. User-1 Mode Regular peripheral access. Tasks at this level may disable interrupts. Supervisor Mode Enables access to all peripheral devices. Reserved Value IS 9 rw Interrupt Stack Control Determines if the current execution thread is using the shared global interrupt stack or a user stack. GW 8 rw Global Address Register Write Permission Determines whether the current execution thread has permission to modify the global address registers.

By compiler convention, global address register A[0] is reserved as the base register for short form loads and stores.

Register A[1] is also reserved for compiler use. Registers A[8] and A[9] are not used by the compiler, and are available for holding critical system address variables. Write permission to global registers A[0], A[1], A[8], A[9] is disabled. Write permission to global registers A[0], A[1], A[8], A[9] is enabled.

CDC mask field is not all set to 1. Call depth counting is temporarily disabled. It is automatically re-enabled after execution of the next Call instruction. Call depth counting is enabled. The first subfield consists of a string of zero or more initial 1 bits, terminated by the first 0 bit. The remaining bits form the second subfield CDC. COUNT which constitutes the call depth count value. The count value is incremented on each Call and is decremented on a Return.

Trap every call call trace mode. Disable call depth counting. When the call depth count CDC. Setting the CDC to B allows no bits for the counter and causes every call to be trapped.

This is used for Call Depth Tracing. Setting the CDC to B disables call depth counting. These bits may be set or cleared as execution side effects of user instructions, typically recording result status. Individual bits can also be used to condition the operation of particular instructions.

Their value User Manual Volume 1 V1. Implementation-specific coprocessor instructions which may use any or all of the eight bits, in a manner that is entirely implementation specific.

This mode may not enable or disable interrupts. IE for the interrupted task. Upper Context If the type does not match the type expected when a context restore operation is performed, a trap is generated. This field is used in conjunction with the PCXO field.

A[10] is used as the stack pointer. The initial contents of this register are usually set by an RTOS when a task is created, which allows a private stack area to be assigned to individual tasks. An automatic switch to the use of the ISP instead of the private stack pointer is implemented in the architecture. IS bit indicates which stack pointer is in effect. When an interrupt is taken and the interrupted task was using its private stack PSW. When an interrupt or trap is taken and the interrupted task was already using the interrupt stack PSW.

The Interrupt Service Routine ISR continues to use the interrupt stack at the point where the interrupted routine had left it. Usually it is only necessary to initialize the ISP once during the initialization routine. However, depending on application needs, the ISP can be modified during execution. Note that there is nothing preventing an ISR or system service routine from executing on a private stack. Temporal Protection is disabled. Temporal Protection is enabled.

Memory protection is controlled through the memory protection register sets. Memory Protection is disabled. Memory Protection is enabled. No FCD trap occurred since the last clear. An FCD trap occurred since the last clear. All other ID registers are described in the product documentation.

Module Revision Number Used for revision numbering. The value of the revision starts at 01H first revision up to FFH. Implementation Specific 22 21 20 19 18 17 16 5 4 3 2 1 0 Implementation Specific 15 14 13 12 11 10 9 8 7 6 Implementation Specific - Field Bits Implementation [ The contents of this register is implementation specific. Implementation Specific 22 21 20 19 18 17 16 5 4 3 2 1 0 Implementation Specific 15 14 13 12 11 10 9 8 7 6 Implementation Specific Field Bits Implementation [ There can be a maximum number of four sets one set includes both a data set and a code set.

Each register set is made up of several range registers also called Range Table Entries. The register pair specifies the lower and upper boundary addresses of the memory range. The need for software updates to CSFRs is usually infrequent.

Implementations are therefore not required to implement hardware structures to avoid hazard conditions that may result from the update of CSFRs. A MTCR instruction that accesses an undefined register location will have no effect. A MFCR instruction that accesses an undefined register location will return undefined data. That model is generally supported by the services of a Real-time Executive or Real-time Operating System RTOS , layered on top of the features and capabilities of the underlying machine architecture.

At the same time the architecture allows for considerable flexibility in the tasking model used. System designers can choose the real-time executive and software design approach that best suits the needs of their application, with relatively few constraints imposed by the architecture. The mechanisms for low-overhead task switching and for function calling within the TriCore architecture are closely related. The state of a task is defined by its context. The context types are: Consists of the upper address registers A[10] to A[15] and the upper data registers D[8] to D[15].

These registers are designated as non-volatile for purposes of function-calling their contents are preserved across calls. A CSA is 16 words of memory storage, aligned on a 16 word boundary.

The fields are a 4-bit segment and a bit offset. Incrementing the pointer offset value by one always increments the EA to the address that is 16 word locations above the previous one. When one of these events or instructions is encountered, the upper or lower context of the task is saved or restored.

The upper context is saved automatically as a result of an external interrupt, trap or function call. The lower context is saved explicitly through instructions. There is an essential difference in the treatment of registers in the upper and lower contexts, in terms of how their contents are maintained.

The lower context registers are similar to global registers in the sense that a interrupt handler, trap handler or called function, sees the same values that were present in the registers just before the interrupt, trap or call.

Any changes made to those registers that are made in the interrupt, trap handler or called function, remains present after the return from the event, since they are not automatically restored as part of the Return From Call RET or Return From Exception RFE semantics.

That means that the lower context registers can be used to pass arguments to called functions and pass return values from those functions. It also means that interrupt and trap handlers must save the original values they find in these registers before using the registers, and to restore the original values before exiting.

The upper context registers are not guaranteed to be static hardware registers. Conceptually, a function call or interrupt handler always begins execution with its own private set of upper context registers. The upper context registers of the interrupted or calling function are not inherited.

A function, trap handler or interrupt handler that reads any of the other upper context registers before writing a value into it, is performing an undefined operation. The following figure Figure shows a simple configuration of CSAs within both context lists. The new value of FCX, which points to the next available CSA, is available immediately for subsequent upper or lower context saves.

The action taken by the trap handler depends on the software implementation. It might issue a system reset for example, if it is determined that the CSA list depletion resulted from an unrecoverable software error. Normally however it extends the free list, either by allocating additional memory or by terminating one or more tasks and reclaiming their CSA call chains. In those cases the trap handler exits with a RFE instruction.

This is necessary to support the FCU trap. If the type does not match the type expected when a context restore operation is performed, a CYTP exception occurs and a context management trap is taken. For a synchronous trap, the A[11] RA is updated with the PC of the instruction which raised the trap. When a lower context save operation is performed the value of A[11] RA is included in the saved context and is placed in the second word of the CSA. This A[11] RA is correspondingly restored by a lower context restore.

CDC consists of two subfields; A call depth counter, and a mask that determines the width of the counter and when it overflows. The Call Depth Counter is incremented on calls and is restored to its previous value on returns.

An exception occurs when the counter overflows. If, when an interrupt or trap is taken, the processor is not using the interrupt stack PSW.

IS bit is then set to one 1 to indicate execution from the interrupt stack. PIE are all part of the interrupt management system. Once the interrupt or trap is handled, the saved lower context is reloaded if necessary and execution of the interrupted task is resumed RFE. On an interrupt or trap the upper context of the current task context is saved by hardware as an explicit part of the interrupt or trap sequence. For small interrupt and trap handlers that can execute entirely within this set of registers saved on the interrupt, no further context saving is needed.

The handler can execute immediately and return. That instruction must be issued before any of the associated registers are modified, but it need not be the first instruction in the handler. Interrupt handlers with critical response time requirements can perform their initial, time-critical processing immediately, using upper context registers.

After that they can execute a BISR and continue with less time-critical processing. The BISR re-enables interrupts, hence its use dividing time critical from less time critical processing. On a function call the entire set of upper context registers are saved by hardware. Furthermore, the saving of the upper context by the CALL instruction happens in parallel with the call jump. In addition, restoring the upper context is performed by the RET Return instruction and takes place in parallel with the return jump.

The calling and called functions must co-operate on the use of the lower context registers. No other state is saved. The called function therefore starts execution with the same context as the caller with the exception of A10 and A This performs a jump to the current return address A11 and loads the previous A11 back from the stack A10 SP. No other state is loaded. The caller function therefore resumes execution with a context modified by the called function.

The calling and called functions must co-operate on the use of all registers. When the context save operation is performed, the first CSA in the free context list CSA3 is pulled off and is placed on the front of the previous context list. The numbers in the figure correspond to the steps listed after the figure. The processor context to be saved is now written into the rest of CSA3. Figure shows the steps taken during the context restore operation.

The numbers in the figure correspond to the following steps: The restored context is then written into the upper or lower context registers. Previous Context PointerPage Each pointer consists of two fields: A 4-bit segment specifier.

A Context Save Area is an address range containing 16 word locations 64 bytes , which is the space required to save one upper or one lower context. Incrementing the pointer offset value by one always increments the Effective Address EA to the address that is 16 word locations above the previous one. This always points to an available CSA. Such restrictions will be detailed in the documentation accompanying a specific TriCore product.

The actual number of additional service providers implemented in a given device is implementation dependent. Interrupt arbitration busses connect the SRNs with the interrupt control units of the service providers. These control units handle the interrupt arbitration and communication with the service provider. Figure Page shows an overview of a typical TriCore interrupt system. A peripheral or other module can have several service request lines, with each one of them connecting to its own individual SRN.

The interrupt request bit can only be set by software. It should be noted however, that the interrupt request can also be set through an external bus master for example. Req … Module N Int. A request status bit shows whether or not the request is active. Besides being activated by the associated module through hardware, each request can also be set or reset through software.

Written value is not stored. No action if CLRR is also set. No action if SETR is also set. No Service Request pending. Service Request is pending. Service Request is disabled. Service Request is enabled. Typically CPU service is initiated. Request Service Provider 1. Request Service Provider 2.

Request Service Provider 3. A Service Request on this priority is never serviced. Service Request, lowest priority. Service Request, highest priority. If hardware attempts to modify SRR during an atomic read-modify-write software operation such as store the software operation succeeds and the hardware operation has no effect. Writing zero to these bits has no effect and these bits always return zero when read. For example, an associated trigger event in a peripheral sets this bit to one and the acknowledgment of the service request by the Service Provider causes this bit to be cleared.

Writing directly to SRR via software has no effect. SRR can be set or cleared either by hardware or by software regardless of the state of the enable bit SRE. Bit SRR is automatically reset by hardware when the service request is acknowledged and serviced. Software can poll SRR to check for a pending service request.

If the SRE bit is set to 0, then the associated interrupt source is disabled. The SRR bit can still be set by hardware or software via the SETR bit , and can be read by software, but if the interrupt source is disabled it will not cause a hardware interrupt to be asserted.

Users can therefore choose whether to handle the event associated with an individual SRN as an interrupt or through software polling. Type-of-Service Control TOS The interrupt system is designed to manage up to four Service Providers for service requests from peripherals or other sources. The TOS bit field is used to select the service provider for a request, indicating whether the service request takes part in the interrupt arbitration of the selected service provider.

The number of service providers for a given device is implementation specific. Each SRPN used by active sources requesting the same service provider must be unique at a given time. This means that no two or more active sources requesting CPU service for example are allowed to use the same SRPN, although they can use the same SRPNs as sources which are requesting another service provider.

The term active source in this context means a source which has its request enable bit SRE set to 1, to allow the request to participate in interrupt arbitrations. Implementations may look at a subrange of SRPN fields. In such an implementation or configuration the SRPN examined fields must be unique within the examined field. The SRPN also identifies the entry into the interrupt vector table or similar structures depending on the nature of the service provider.

Unlike other interrupt systems the TriCore vector table provides an entry for each priority number, not for a specific interrupt source. In this way the vector table is de-coupled from the peripherals and a single peripheral can have multiple entry points for different purposes depending on its priority at a given time.

With the 8-bit SRPN, the interrupt arbitration scheme permits up to sources to be active at one time. The number of Interrupt Control Units depends on the number of service providers implemented in a TriCore device. Each ICU controls its associated interrupt arbitration bus and manages the communication with its service provider.

This register and the operation of the ICU is described in the sections which follow. The interrupt system must therefore determine which request has the highest priority each time multiple requests are received.

The interrupt system uses a scheme that performs the arbitration in parallel to normal CPU operation. The Interrupt Control Unit ICU controls this scheme, which takes place in one or more cycles using the interrupt arbitration bus. The detailed arbitration scheme is implementation specific.

The ICU automatically starts an arbitration when a new interrupt request is detected. At the end of the arbitration the ICU has determined the service request with the highest priority number. This node then resets its service request flag SRR. After sending the acknowledge, the ICU sets PIPN to 00H no valid pending request and automatically starts a new arbitration to check whether there is another pending interrupt request.

If there is then the priority number of this request is written to PIPN at the end of this arbitration. The CPU is in the process of entering an interrupt or trap service routine. The CPU is operating on non-interruptible trap services. The CPU is executing a multi-cycle instruction. The CPU responds to the interrupt request only when these conditions are no longer true.

In this way the PIPN field therefore reflects the pending service request with the highest priority. This can for example, be used for software polling techniques to determine high priority requests while keeping the interrupt system globally disabled.

If a new service request is generated by an SRN while an arbitration is in progress, this request has to wait until at least the end of that arbitration. If the processor was not previously using the interrupt stack PSW.

The stack pointer bit is then set for using the interrupt stack: Memory protection using the interrupt memory protection map is enabled: CDC is cleared, and the call depth limit selector is set for Write permission to global registers A[0], A[1], A[8], A[9] is disabled: The interrupt system is globally disabled: The interrupt vector table is accessed to fetch the first instruction of the ISR.

Global register write permission is disabled PSW. This ensures that all traps and interrupts must assume they do not have write access to the registers controlled by PSW. It is up to the user to enable the interrupt system again and optionally modify the priority number CCPN to implement interrupt priority levels or handle special cases. CCPN to a new value, and saves the lower context of the interrupted task.

The interrupt enable bit ICR. This avoids pipeline side effects and eliminates the need for an ISYNC synchronize instruction stream following these instructions. The values in these respective bits are used as follows: IE to restore the state of this bit. The interrupted routine then continues. The Interrupt Vector Table is stored in code memory. This address is loaded in the program counter. Interrupt vectors are ordered in the table by increasing priority. With this arrangement, it is possible to have multiple Interrupt Vector Tables and switch between them by changing the contents of the BIV register.

Execution of the ISR begins at this address. Due to this operation, it is recommended that bits [ Note that bit 0 of the BIV register is always 0 and cannot be written to instructions have to be aligned on even byte boundaries. If an interrupt handler is very short it may fit entirely within the 8 words available in the vector code segment. Otherwise the code stored at the entry location can either span several vector entries, or should contain some initial instructions followed by a jump to the rest of the handler.

The default on power-up is fixed to H, however the BIV register can be written to using the MTCR instruction during the initialization phase of the system, before interrupts are enabled. It is also possible to have multiple interrupt vector tables and switch between them simply by modifying the contents of the BIV register.

Spanning eliminates the need of a jump to the rest of the interrupt handler if it would not fit into the available eight words between entry locations. Note that priority numbers relating to entries occupied by a spanned service routine must not be used for any of the active Service Request Nodes SRNs which request service from the same service provider.

In Figure Page , vector locations three and four are covered through the service routine for entry two. Therefore these numbers must not be assigned to SRNs requesting CPU service, although they can be used to request another service provider. The next available vector entry is now entry five. Use of this technique increases the range of priority numbers required in a given system, but the size of the vector table must be adjusted accordingly.

These groups are easily created with the TriCore interrupt system architecture. This blocks all further interrupts from being serviced until the interrupt system is either enabled again through software, or the service routine is terminated with the RFE Return From Exception instruction. This will be one ICE. This includes a re-occurrence of the current interrupt; i. A potential problem that is easily overcome in the TriCore architecture is that application requirements often require interrupt requests of similar significance to be grouped together in such a way that no request in that group can interrupt the ISR of another member of the same group.

Creating these Interrupt Priority Groups is easily accomplished in the interrupt system. For a defined group of interrupt requests, the software of their respective service routines sets the CCPN to the number of the highest SRPN used in that group, before enabling the interrupt system again. Figure shows an example. Every time one of the interrupts from group one is serviced, the service routine sets the CCPN to 12, the highest number in that group, before re-enabling the interrupt system.

Every time one of the interrupts from group two is serviced, the service routine sets the CCPN to 17 before reenabling the interrupt system. If interrupt 14 is serviced for example, it can only be interrupted by requests with a priority number higher than 17, but not through a request from its own priority group or requests with lower priority.

One can see the flexibility of this system and its superiority over systems with fixed priority levels. Setting the CCPN to the maximum number in each service routine has the same effect as not enabling the interrupt system again; i.

The flexibility for interrupt priority levels ranges from all interrupts being in one group, to each interrupt request building its own group, and all possible combinations in between. For example, an interrupt is placed on a very high priority because response time and reaction to an event is critical, but further operations in that service routine can run on a lower priority. In this instance the service routine would be divided into two parts, one containing the critical actions, the other part the less critical ones.

The priority of the interrupt node is first set to the high priority, so that when the interrupt occurs the necessary actions are carried out immediately. The priority level of this interrupt is then lowered and the interrupt request bit is set again via software indicating a pending interrupt while still in the service routine.

Returning to the interrupted program terminates the high priority service routine. The pending interrupt is serviced when the CPU priority is lower than its own priority.

After entering the service routine, which is now at a different address in the program memory, the outstanding but low-priority actions of the interrupt are performed. To prevent any interruption the TriCore architecture allows the priority level of the service request to be raised within the ISR, and also allows interrupts to be completely disabled. This can be achieved simply by assigning different Service Request Priority Numbers SRPNs at different times to an interrupt source depending on the application needs.

Usually the ISR for that interrupt executes different code depending on its priority. In traditional interrupt systems, the ISR would have to check the current priority of that interrupt request and perform a branch to the appropriate code section, causing a delay in the response to the request.

In the TriCore system however, the interrupt will automatically have different vector entries for the different priorities. An extra check and branch in the ISR is not necessary, therefore the interrupt latency is reduced. The use of different priority numbers for one interrupt has to be taken into consideration when creating the vector table.

Once the interrupt request bit in a service request control register is set, there is no way to distinguish between a software-posted interrupt request and a hardware interrupt request. For that reason it is generally advisable to use Service Request Nodes and interrupt priority numbers for software-posted interrupts that are not used for hardware interrupts, such as interrupts which are triggered by a peripheral module. However the number of hardware SRNs available in a given system for such purposes depends on the application requirements.

To support the use of software-posted interrupts, principally for RTOS code, the architecture provides a number of Service Request Nodes which are intended solely for the purpose of software-posting. They are not connected to any peripheral or any other module on the chip, and the service request flag can only be set by software.

ISRs whose actions affect the launching of software-managed tasks post a software interrupt request at priority level one to signal the change. There is no need for an exit function to check whether the ISR is returning to the background task level or to a lower priority ISR that it interrupted, in order to determine when to invoke the task dispatch function.

When there is a pending interrupt at a priority higher than the return context for the current interrupt, this interrupt will then be serviced. When a return to the background task level is performed the software-posted interrupt at priority level one will automatically be recognized and serviced.

The BIV register holds the base addresses for the interrupt vector tables. Special instructions control the enabling and disabling of the interrupt system. See the relevant documentation for a specific TriCore product implementation. It indicates the priority number of the pending service request. PIPN is set to 0 when no request is pending, and at the beginning of each new arbitration process. No valid pending request. Request pending, lowest priority. Request pending, highest priority. IE is cleared to 0 when an interrupt is taken, and is restored to the previous value when the ISR executes an RFE instruction to terminate itself.

Interrupt system is globally disabled. Interrupt system is globally enabled. When an interrupt is accepted, the entry address into the interrupt vector table is generated from the priority number taken from the PIPN of that interrupt, left shifted by five bits, and then ORd with the contents of the BIV register.

The left-shift of the interrupt priority number results in a spacing of 8 words 32 bytes between the individual entries in the vector table. Because of the simple ORing of the left-shifted priority number and the contents of the BIV register, the alignment of the base address of the vector table must be to a power of two boundary, dependent on the number of interrupt entries used.

For the full range of interrupt entries an alignment to an 8 KByte boundary is required. If fewer sources are used, the alignment requirements are correspondingly relaxed. Traps are always active; they cannot be disabled by software action.

Each class has its own trap handler, accessed through a trap vector of 32 bytes per entry, indexed by the hardware-defined trap class number. Within each class, specific traps are distinguished by a Trap Identification Number TIN that is loaded by hardware into register D[15] before the first instruction of the trap handler is executed.

The trap handler must test and branch on the value in D[15] to reach the subhandler for a specific TIN. Traps can be further classified as synchronous or asynchronous, and as hardware or software generated.

These are explained after the following table which lists the trap classes, summarising and classifying the pre-defined set of specific traps within each class. In the following table: HW Virtual Address Fill.

HW Virtual Address Protection. Page 2 MPR Synch. HW Memory Protection Read. Page 3 MPW Synch. HW Memory Protection Write. Page 4 MPX Synch. HW Memory Protection Execution. Page 5 MPP Synch. Page 6 MPN Synch. Page 3 OPD Synch. HW Invalid Operand specification. Page 4 ALN Synch. HW Data Address Alignment. Page 5 MEM Synch. Page 2 CDO Synch. HW Call Depth Overflow. Page 3 CDU Synch. HW Call Depth Underflow. Page 4 FCU Synch. Page User Manual Volume 1 V1.

RFE with non-zero call depth. Page 2 DSE Synch. Page 3 DAE Asynch. SW Sticky Arithmetic Overflow. Page SW System Call. Page Non-Maskable Interrupt. The range of values that can be specified is 0 to , inclusive. The instruction causing the trap is known precisely. The trap is taken immediately and serviced before execution can proceed beyond that instruction.

Some result indirectly from instructions that have been previously executed, but the direct association with those instructions has been lost. The difference between an asynchronous trap and an interrupt is that asynchronous traps are routed via the trap vector instead of the interrupt vector. They can not be masked and they do not change the current CPU interrupt priority number.

In most, but not all cases, the exception conditions are associated with the attempted execution of a particular instruction. Examples User Manual Volume 1 V1. CCPN field is not updated. The vectors are made up of a number of short code segments, evenly spaced by eight words.

If a trap handler is very short it may fit entirely within the eight words available in the vector code segment. If it does not fit the vector code segment then it should contain some initial instructions, followed by a jump to the rest of the handler. The trap identifier has two components: For a synchronous trap, the return address is the PC of the instruction that caused the trap.

For an asynchronous trap, the return address is that of the instruction that would have been executed next, if the asynchronous trap had not been taken. The return address for an interrupt follows the same rule. It can be assigned to any available code memory. This arrangement makes it possible to have multiple Trap Vector Tables and switch between them by changing the contents of the BTV register.

When a trap event occurs, a trap identifier is generated by the hardware detecting the event. Because of this operation, it is recommended that bits [7: Note that bit 0 of the BTV register is always 0 and can not be written to instructions have to be aligned on even byte boundaries.

If a trap handler TSR is very short, it may fit entirely within the eight words available in the Trap Vector Table entry. Otherwise, the code at the entry point must ultimately cause a jump to the rest of the TSR residing elsewhere in memory.

The return address in A[11] is updated. The TIN is loaded into D[15]. The stack pointer bit is set for using the interrupt stack: The current Protection Register Set is set to 0: The trap vector table is accessed to fetch the first instruction of the trap handler.

Although traps leave the ICR. CCPN unchanged, their handlers still begin execution with interrupts disabled. They can therefore perform critical initial operations without interruptions, until they specifically re-enable interrupts. For the non-recoverable FCU trap, the initial state is different. The upper context cannot be saved. Only the following states are guaranteed: The trap vector table is accessed to fetch the first instruction of the FCU trap handler.

The following internal Protection Traps are defined: A table of instructions which are restricted to Supervisor mode or User-1 mode, is supplied in the Instruction Set chapter of Volume 2 of this manual.

T instruction does not lie within any range with read permissions enabled. T instruction does not lie within any range with write permissions enabled. Instruction errors include errors in the instruction opcode, in the instruction operand encodings, or for memory accesses, in the operand address. An invalid opcode is one that does not correspond to any instruction known to the implementation. An unimplemented opcode corresponds to a known instruction that is not implemented in a given hardware implementation.

The instruction may be implemented via software emulation in the trap handler. Example UOPC conditions are: An external coprocessor instruction if the external coprocessor is not present. The OPD trap may also be raised for other cases where operands are invalid. Implementations are not architecturally required to raise this trap, and may treat invalid operands in an implementation defined manner. An ALN trap is also raised when the size, length or index of a circular buffer is incorrect.

It must also document any other implementation specific MEM traps it will raise. Architectural constraints which will raise the MEM trap are: The operation responsible for the context save completes normally and then the FCD trap is taken.

If the operation responsible for the context save was the hardware interrupt or trap entry sequence, then the FCD trap handler will be entered before the first instruction of the original interrupt or trap handler is executed. The return address for the FCD trap will point to the first instruction of the interrupt or trap handler.

The FCD trap handler is normally expected to take some form of action to rectify the context list depletion. The nature of that action is OS dependent, but the general choices are to allocate additional memory for CSA storage, or to terminate one or more tasks, and return the CSAs on their call chains to the free list. A third possibility is not to terminate any tasks outright, but to copy the call chains for one or more inactive tasks to uncached external or secondary memory that would not be directly usable for CSA storage, and release the copied CSAs to the free list.

In that instance the OS task scheduler would need to recognize that the inactive task's call chain was not resident in CSA storage, and restore it before dispatching the task. In addition, it is possible that an asynchronous trap condition, such as an external bus error, will be reported after the FCD trap has been taken, interrupting the FCD trap handler and using one more CSA. Therefore, to avoid the possibility of a context list underflow, the free context list must include a minimum of two CSAs beyond the one pointed to by the LCX register.

If the bit is found to be set, the asynchronous trap handler must avoid making any calls, but should queue itself in some manner that allows the OS to recognize that the trap occurred. It should then carry out an immediate return, back to the interrupted FCD trap handler. COUNT at its maximum value.

A call depth underflow does not necessarily reflect a software error in the currently executing task. An OS can achieve finer granularity in call depth counting by using a deliberately narrow Call Depth Counter, and incrementing or decrementing a separate software counter for the current task on each call depth overflow or underflow trap. A program error would be indicated only if the software counter were already zero when the CDU trap occurred.

The FCU trap is also taken if any error is encountered during a context save or restore operation. The context operation cannot be completed.

In failing to complete the context save or restore, architectural state is lost, so the occurrence of an FCU trap is a non-recoverable system error. The FCU trap handler should ultimately initiate a system reset. This trap indicates a system software error kernel or OS in task setup or context switching among software managed tasks SMTs. No software error or combination of errors in a user task can generate this condition, unless the task has been allowed write permission to the context save areas which, in itself, can be regarded as a system software error.

UL bit, is incorrect for the type of restore attempted; i. As with the CSU trap, this indicates a system software error in context list management. The return from an interrupt or trap handler should normally occur within the body of the interrupt or trap handler itself, or in code to which the handler has branched, rather than code called from the handler. If this is not the case there will be one or more saved contexts on the residual call chain that must be popped and returned to the free list, before the RFE can be legitimately issued.

In the case of an error during the data load phase of a data cache refill. There are implementation-dependent registers for DSE which can be interrogated to determine the source of the error more precisely. Refer to the User's Manual for a specific TriCore implementation for more details. Generally this means an error returned on the system bus from a peripheral or external memory. This DAE trap is raised when: There is an error caused by a cache management instruction. There is an error caused by a cache line writeback.

There are implementation-dependent registers for DAE which can be interrogated to determine the source of the error more precisely. Examples of typical errors that can cause a CAE trap are unimplemented coprocessor instructions and arithmetic errors as found in the Floating Point Unit for example. CAE is shared amongst all coprocessors in a given system.

A trap handler must therefore inspect all coprocessors to determine the cause of a trap. The trap is synchronous to the erroneous instruction.

A PIE trap is raised if any element within the fetch group contains an unrecoverable error. Hardware is not required to localise the error to a particular instruction.

More DSE guidance

Holder to a refund, provided that the required information is timely furnished to the IRS. This scenario is indicated by posting a software interrupt at the interrupt level associated with the Breakpoint.

Closed On:

Figure Page shows an overview of a typical TriCore interrupt system. Holder would be ordinary loss to the extent of interest that same holder included in income in the current or previous taxable years in respect of the securities, and thereafter, would be capital loss.

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